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Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /NPU_HE /NPUHE_CMD

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Interpret as NPUHE_CMD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRANSITION_TO_RUNNING_STATE)TRANSITION_TO_RUNNING_STATE 0 (CLEAR_IRQ)CLEAR_IRQ 0 (CLOCK_Q_ENABLE)CLOCK_Q_ENABLE 0 (POWER_Q_ENABLE)POWER_Q_ENABLE 0 (STOP_REQUEST)STOP_REQUEST 0CLEAR_IRQ_HISTORY

Description

Command Register

Fields

TRANSITION_TO_RUNNING_STATE

Write 1 to transition the NPU to running state. Writing 0 has no effect.
CLEAR_IRQ

Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect.
CLOCK_Q_ENABLE

Write 1 to this bit to enable clock off using Clock Q-interface and enable the master clock gate.
POWER_Q_ENABLE

Write 1 to this bit to enable power off using Power Q-interface.
STOP_REQUEST

Write 1 to this bit to request STOP after completing any already-started commands.
CLEAR_IRQ_HISTORY

Clears the IRQ history mask. When bit [k] is set, then the corresponding bit [k] of the NPUHE_STATUS[IRQ_HISTORY_MASK] field is cleared.

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data